The present invention relates, in general, to the field of data processor timers and methods. More particularly, the present invention relates to a sharable prescaled timer and method for a microprocessor or microcomputer having a free running counter.
Current generation microprocessors (MPU's) and microcomputers (MCU's) have greatly increased bus speeds over their predecessors of just a short time ago. These very high operating speeds require a high frequency oscillator and clock generator for generating the central processing unit (CPU) cycle clock (E clock). This E clock will then be used to drive a free-running counter timer. Typically however, these MPU/MCU's will have interrelated subsystems and timing functions with independent and slower timing constraints which require, therefore, lower clocking frequencies.
Latest generation MPU/MCU's, may also incorporate a prescaler or multistage divider between the system E clock and free-running counter chain. This, in turn, has necessitated the replication of timer chains for each of the slower operating interrelated subsystems and timing functions (e.g. real time interrupt, watchdog timer, etc.) which must remain independent of the prescale factor utilized. Unfortunately, such additional timer chains utilizing cascade connected flip flops, each of which require a considerable amount of on-chip area, mean that such replicated timer chains are provided only at great expense in silicon area and concomitant cost.